1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having its standby current reduced.
2. Description of Related Art
In a semiconductor device such as a PC-RAM (Phase Change Random Access Memory) or a Re-RAM (Resistance Random Access Memory), a diode can be used as a selection element for selecting a specific memory cell from a plurality of memory cells. In this case, the diode is connected to a memory element in series, and a voltage is applied to the diode such that it is forward biased when its corresponding word line is selected and reverse biased when the word line is not selected. With this configuration, only when a word line is selected, a current flows through a memory element from a bit line corresponding to the selected word line. An example of a phase change memory device employing the above configuration is disclosed in Japanese Patent Application Laid-open No. 2009-4000.
A configuration for forward biasing or reverse biasing a diode is explained below in detail.
In a semiconductor device in which a diode is used as a selection element for selecting a memory cell, two transistors including a global MOS transistor and a pre-charge MOS transistor are provided for each word line. The gates of the two transistors are connected to a word line. The global MOS transistor is configured to be turned ON when the word line is selected and turned OFF when the word line is not selected. On the other hand, the pre-charge MOS transistor is configured to be turned OFF when the word line is selected and turned ON when the word line is not selected.
The source of the global MOS transistor is connected to a ground line to which a ground potential VSS is supplied, and the drain of the global MOS transistor is commonly connected to cathodes of a plurality of diodes arranged in the word line direction. Hereinafter, a signal line connecting the drain of the global MOS transistor and the cathode of each of the diodes is referred to as “drain line”. The source of the pre-charge MOS transistor is connected to a power supply line to which a drain potential VDR is supplied, and the drain of the pre-charge MOS transistor is connected to one end of the drain line. The drain potential VDR is a potential that becomes equal to or higher than a write potential of a bit line when writing data in a memory cell and equal to or higher than a read potential when reading data from a memory cell.
With the above configuration, when a word line is selected, the ground potential VSS is supplied to the cathode of each of the diodes connected to the word line through the drain line and the global MOS transistor corresponding to the word line. Therefore, if the write potential or the read potential is supplied to a bit line, each of the diodes is forward biased. On the other hand, the drain potential VDR is supplied to the cathode of each of the diodes connected to a non-selected word line through the drain line and the pre-charge MOS transistor corresponding to the non-selected word line. Therefore, each of the diodes is reverse biased.
However, the above semiconductor device has a problem that it is difficult to suppress a standby current of a memory mat to a value equal to or smaller than a value of standard. That is, in the above semiconductor device, an off-leak current (sub-threshold current) of the global MOS transistor or a short circuit (defect) of the ground line or the source of the global MOS transistor can cause an increase of the standby current. However, it is difficult to suppress or prevent these currents, and as a result, it is difficult to suppress the standby current of the memory mat to a value equal to or smaller than the value of standard. Details on this aspect are explained below.
In a memory mat, a considerably large number of global MOS transistors are included, for example, 2×109 transistors are included in the case of a 2-Gb product. Therefore, in order to suppress the standby current of the entire memory mats to a value equal to or smaller than the value of standard, it is necessary to suppress the off-leak current of each of the global MOS transistors to a considerably small value. However, in practice, it is a difficult task to be accomplished.
Further, even one place where the ground line or the source of the global MOS transistor is short-circuited can cause the standby current of the memory mat to exceed the value of standard. However, as described above, because there are a considerably large number of global MOS transistors in the memory mat and there are a large number of ground lines, it is difficult in practice to prevent the short circuits at all the places.